1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more specifically to a semiconductor device having an active region in a semiconductor layer formed on an insulator layer and a manufacturing method thereof.
2. Description of the Background Art
In the field of semiconductor device manufacture, an integrated circuit aimed at increasing integration density or improving functions by stacking active devices in a three-dimensional manner is a so-called three-dimensional integrated circuit. In implementation of such a three-dimensional integrated circuit, a technique for forming a so-called SOI (Silicon On Insulator) structure in which a monocrystalline semiconductor layer is formed on an insulator layer plays a significant role.
A number of methods for forming a monocrystalline silicon layer on an insulator layer have been proposed, such as a method of forming an oxide film in a substrate by implanting oxygen ions into a monocrystalline silicon substrate (SIMOX), melt recrystallization method by which a non-monocrystalline semiconductor on an insulator layer is heated by a heater, melt recrystallization method by means of energy beam irradiation, etc. Especially, the melt recrystallization by energy beam irradiation is indispensable for forming a three-dimensional integrated circuit device. The three-dimensional integrated circuit device is an integrated circuit which is formed into a multilayer structure by stacking integrated circuit layers with an insulator layer therebetween, which is conventionally a single layer, and aimed at great improvements in function and integration density compared to conventional two-dimensional integrated circuit devices.
The melt recrystallization method is a method of forming a monocrystalline layer by recrystallizing a polycrystalline or amorphous semiconductor layer on an insulator layer by means of heat-treatment. A high power laser or an electron beam may be used for the energy beam, but the laser is mainly used as it is easier to operate. The temperature distribution inside a molten semiconductor should be controlled so that recrystallization is initiated from an arbitrary location in order to form a monocrystalline semiconductor layer by the melt recrystallization method by means of laser irradiation. A number of methods have been suggested for controlling the distribution of temperature, and in any method, recrystallization starts from a position of low temperature and proceeds toward high temperature locations. This results in the formation of sub-grain boundaries or grain boundaries after the high temperature locations are recrystallized. A melt recrystallization method by means of laser irradiation using an anti reflection film for controlling the temperature is described in detail, for example, in U.S. Pat. No. 4,822,752. A description will be provided on how a monocrystalline semiconductor layer is formed by such a melt recrystallization method by means of laser irradiation using an anti reflection film.
FIG. 42 is a sectional perspective view showing a structure of a semiconductor device in a manufacturing process in accordance with a conventional melt recrystallization method by laser irradiation. FIGS. 43 to 45 are sectional views showing structures for illustrating the essential steps of the melt recrystallization method. The melt recrystallization method which will be described in the following is a method using an anti reflection film for the purpose of arbitrarily controlling the temperature distribution in a molten semiconductor layer.
Referring to FIGS. 42 and 43, an insulating layer 2 formed of a silicon oxide film is formed on the surface of a silicon monocrystalline substrate 1. An opening 15 is formed in a prescribed region of insulating layer 2. Opening 15 constitutes a seed portion. A non-monocrystalline semiconductor layer, in other words a polycrystalline silicon layer 13 is formed on the surface of insulating layer 2 and inside opening 15. Anti reflection films 14 of a prescribed shape are also formed on the surface of polycrystalline silicon layer 13. A silicon nitride film (Si.sub.3 N.sub.4) is for example used for anti reflection film 14. Anti reflection films 14 are each formed at a position an approximately equal distance separated from opening 15 formed in insulating layer 2 (see FIG. 42). Though not shown, a thin cap film may be formed entirely over the surfaces of polycrystalline silicon layer 13 and anti reflection film 14 for the purpose of keeping the surfaces from deforming in the process of recrystallization. Opening 15 is filled with polysilicon which is a non-monocrystalline semiconductor. The crystalline orientation of polycrystalline silicon layer 13 to be recrystallized is therefore controlled based on silicon monocrystalline substrate 1.
The reflectivity of a silicon nitride film forming anti reflection film 14 periodically indicates the maximum value and 0 depending upon its thickness. Taking advantage of this effect, a silicon nitride film having a thickness giving a reflectivity of 0 is used for the anti reflection film. According to this conventional example, silicon oxide film having a thickness of about 600 .ANG. (60 nm) is used for anti reflection film 14. Therefore, in FIGS. 42 and 43, anti reflection films 14 selectively formed on the surface of polycrystalline silicon layer 13 has zero reflectivity to laser light 70, in other words absorbs almost all the incident light. In contrast, the region in which the thickness of anti reflection film is 0, in other words the region in which the surface of polycrystalline silicon layer 13 is exposed has a reflectivity of about 40% to the laser light 70. This causes the laser light irradiated upon the entire surface of polycrystalline silicon layer 13 to be more absorbed at the lower portion of anti reflection film 14, and the region is heated to a higher temperature. The laser light 70 used has a wave length of about 488 nm, and a beam diameter in the range of about 120-180 .mu.m. A silicon oxide film having a thickness in the range between 1-3 .mu.m is used for insulating layer 2, and polycrystalline silicon layer 13 used as the non-monocrystalline semiconductor layer has a thickness of about 0.6 .mu.m. The width of anti reflection film 14 is about 5 .mu.m, and the spacing between the films is about 10 .mu.m.
Laser light 70 moves at a constant speed while being irradiated upon the surface of polycrystalline silicon layer 13. Polycrystalline silicon layer 13 irradiated with the laser light 70 has its temperature increased, and melts. The temperature distribution of polycrystalline silicon layer 13 at that time is shown in FIG. 46. FIG. 46 is a representation showing the temperature distribution for illustrating the relation between positions on the surface of polycrystalline silicon layer 13 and inside temperatures. As can be seen from the illustrated temperature distribution, the inside temperature of polycrystalline silicon layer 13 is higher at the lower portion of anti reflection film 14. In other words, the inside temperature of polycrystalline silicon layer 13 is lower in the vicinity of opening 15.
Referring to FIG. 44, after the passage of the laser light 70, melted polycrystalline silicon layer 13 is cooled, has its temperature gradually decreased, and starts recrystallizing (solidifying) from the region of lower temperatures. As shown in the temperature distribution of FIG. 46, the inside temperature of polycrystalline silicon layer 13 is low in the vicinity of opening 15, and in the cooling process recrystallization of polycrystalline silicon layer 13 is initiated using as a seed portion 16 polycrystalline silicon layer 13 which fills opening 15. Seed portion 16 is connected to silicon monocrystalline substrate 1. Therefore, a monocrystalline silicon region 3a having the same crystal orientation as silicon monocrystalline substrate 1 expands from seed portion 16 toward the circumference thereof.
Referring to FIG. 45, the polycrystalline silicon layer completely recrystallized changes into a homogenous monocrystalline silicon layer 3. Anti reflection films 14 are then removed away.
When a monocrystalline semiconductor layer is formed in such a way, the lower portion of the anti reflection film has a higher temperature, and, therefore, recrystallization of the polycrystalline silicon layer starts from the seed portions between the anti reflection films and proceeds toward the lower portions of the anti reflection films. This results in the collision of crystals developed from the opposing sides of the anti reflection film. Sub-grain boundaries 31 emerge at the positions where the developed crystals collide against each other (see FIG. 45).
Although each semiconductor layer portion between anti reflection films is monocrystalline, their crystalline orientations are, to be exact, slightly shifted from each other because adjacent semiconductor layers with anti reflection films therebetween separately grow into crystal. Sub-grain boundaries 31 are formed as the boundary portion. Such sub-grain boundaries 31 emerge under the anti reflection films, and, therefore, their positions can be controlled. Even when recrystallization is conducted without forming the seed portions (openings), the semiconductor layer portions between anti reflection films are formed into monocrystal. However, since nothing defines the orientation of the monocrystal in this case, the adjacent semiconductor layers with the anti reflection films therebetween have different crystal orientations. More specifically, the boundaries under the anti reflection films are formed as grain boundaries.
Effects given by such grain boundaries or sub-grain boundaries on the properties of active devices formed in a monocrystalline silicon layer are reported in Japanese Journal of Applied Physics Vol. 22, 1983, Supplement 22-1 pp. 217-221, or Extended Abstracts of the 17th Conference on Solid State Devices and Materials, Tokyo, 1985, pp. 147-150. According to the documents, increase of current leakage, etc. are induced in the presence of grain boundaries in the channel region of an MOS field effect transistor. The active region of a transistor is therefore defined so as to exclude the existence of grain boundaries or sub-grain boundaries in the channel region of an MOS field effect transistor according to a prior art technique disclosed in IEEE Electron Device Letter, Vol. EDL-7, No. 3, March 1986, pp. 193-195. More specifically, as will be described later, a silicon nitride film 181 is patterned so as to exclude a region of sub-grain boundaries 31 in a monocrystalline silicon layer 3 as shown in FIG. 50. An active region is formed in a region of monocrystalline silicon layer 3 which is free of the sub-grain boundaries under silicon nitride film 181.
It has been established that the presence of sub-grain boundaries or grain boundaries do not give any adverse effect on the properties of active devices even with sub-grain boundaries or grain boundaries existing other than in a channel region, for example, in a source/drain region, because the source/drain region containing an impurity of high concentration has its resistance reduced, provided that sub-grain boundaries or grain boundaries do not exist at the pn junction.
The surface of monocrystalline silicon layer 3 formed by a melt recrystallization method using such an anti reflection film as described above waves and is roughly stepped as shown in FIG. 45. FIG. 47 is a graphic representation showing the result of the measurement as to the surface roughness of monocrystalline silicon layer 3 shown in FIG. 45. The measurement represents the case in which the thickness of a recrystallized semiconductor layer is 550 nm. In this case, the steps and recesses formed on the surface is each as large as about .+-.60 nm (0.06 .mu.m) or more. The surface of recrystallized monocrystalline silicon layer 3 waves and is stepped because the surface of molten polycrystalline silicon layer 13 is partially covered with anti reflection films 14. More specifically, when polycrystalline silicon layer 13 is recrystallized, the layer underlying anti reflection film 14 has a higher temperature than the region between anti reflection films 14. Therefore, the region between anti reflection films 14 solidifies first and the lower portion of anti reflection films 14 later. The higher the temperature of the melt, the lower its surface tension gets, and, therefore, portion 3a to solidify first takes a stepped form, while portion 3b to solidify later takes a recessed form in the solidification of monocrystalline silicon layer 3 as shown in FIG. 45. In the surface of monocrystalline silicon layer 3, steps and recesses are produced in correspondence to the positions of anti reflection films 14 as shown in FIG. 45. The width of anti reflection film 14 is about 5 .mu.m, with the spacing between the films being about 10 .mu.m, the recess or step exists about for every 15 .mu.m. The formation of such recesses and steps on the surface gives rise to various problems in the process of forming active devices on the surface of monocrystalline silicon layer 3, thus resulting in uneven performances achieved by devices.
It is known that in forming devices on such a monocrystalline semiconductor layer on an insulator layer, reducing the thickness of the semiconductor layer to 0.1 .mu.m or smaller improves the performances of the devices. The film thickness however can not be reduced in the presence of the steps and recesses on the surface of the monocrystalline semiconductor layer as described above.
Polishing the surface of the monocrystalline semiconductor layer can be taken as an approach for reducing the steps and recesses of the surfaces as stated above, especially, a so-called rigid polishing method using a hard body such as SiO.sub.2 as a surface plate instead of a polishing pad is most prevailing among various methods of reducing surface steps and recesses. When a monocrystalline semiconductor layer was polished by this rigid polishing method it was confirmed by optical microscopic and scanning electron microscopic observations that the steps and recesses of the surface of the monocrystalline semiconductor layer are each reduced to as large as several tens .ANG. and smaller and takes a form of mirror surface.
However, even when active devices are formed in a monocrystalline semiconductor layer so that grain boundaries or sub-grain boundaries do not exist in the active region as described above, the properties of the active devices are still significantly uneven. Inspections were therefore made as to the crystal property of a monocrystalline semiconductor layer after usual process of forming active devices, and the inventors found new defects in the crystal which was not discovered immediately after the formation of the monocrystalline semiconductor layer.
FIGS. 48-58 are partially sectional views showing steps in their order in a method of manufacturing a CMOS transistor using a conventional SOI structure. Referring to these figures, a description will be provided on a method of forming an MOS transistor utilizing a conventional SOI structure and associated problems.
Referring to FIG. 48, the state of a monocrystalline semiconductor layer of SOI structure immediately after its formation is shown. An insulating layer 2 of SiO.sub.2 is formed on a silicon monocrystalline substrate 1. A monocrystalline silicon layer 3 is formed on insulating layer 2. Sub-grain boundaries 31 exist at constant intervals as described above on monocrystalline silicon layer 3.
Referring to FIG. 49, an underlying oxide film 17 is formed on monocrystalline silicon layer 3 by means of heat oxidation. Underlying oxide film 17 is formed for the purpose of removing the surface defects of monocrystalline silicon layer 3. Underlaying oxide film 17 is also used as an underlying oxide film in forming element isolation regions in a subsequent step. A silicon nitride film 18 is then formed on the entire surface of underlying oxide film 17 by means of CVD (Chemical Vapor Deposition). The thicknesses of underlying oxide film 17 and silicon nitride film 18 are 500 .ANG. and 1000 .ANG., respectively.
Referring to FIG. 50, a resist film 45 is formed only on the element formation region using a photolithography technique. The silicon nitride film is removed using a patterned resist film 45 as a mask, leaving a silicon nitride film 181 in place.
Referring to FIG. 51, a resist film 42 is formed in a pMOS transistor formation region. Using resist films 42 and 45 as masks, boron (B) ions are implanted into monocrystalline silicon layer 3 through underlying oxide film 17. The amount of boron implanted at this time is about 3.times.10.sup.13 cm.sup.-2.
Referring to FIG. 52, after removal of resist films 42 and 45, a thick oxide film 171 is formed by heat-oxidation using silicon nitride film 181 as a mask. At that time, a p.sup.+ impurity region 33 is formed as a channel cut layer in the region in which the boron is implanted.
As shown in FIG. 53, after removal of silicon nitride film 181, a resist film 4 is formed only in the region for forming a pMOS transistor. Using resist film 4 as a mask boron ions are implanted into monocrystalline silicon layer 39 in the region for forming an nMOS transistor.
A p.sup.- region 34 is thus formed as shown in FIG. 54. Then, using as a mask resist film 4 formed only in the nMOS transistor formation region, phosphorus (P) ions are implanted into monocrystalline silicon layer 39 in the pMOS transistor formation region. The amounts of boron and phosphorus to be implanted at that time are determined depending upon threshold voltages set for nMOS and pMOS transistors, respectively.
An n.sup.- region 35 is formed as shown in FIG. 55. After removal of resist film 4, underlying oxide film 17 is removed away. A gate oxide film 51 is then formed. The thickness of the gate oxide film is several hundred .ANG.. A polycrystalline silicon layer for a gate electrode as thick as about 3000 .ANG. is formed on the entire surface by CVD method. The polycrystalline silicon layer is doped with an impurity for reducing its resistance, and then the polycrystalline layer is selectively removed away using a patterned resist film 44 as a mask. A gate electrode 61 is thus formed.
As shown in FIG. 56, a resist film 42 is formed only in the PMOS transistor formation region. Using resist films 42 and 44 as masks, arsenic (As) ions are implanted into the source and drain formation region of an NMOS transistor.
In addition, as shown in FIG. 57, a resist film 4 is formed only in the region of NMOS transistor in which an n.sup.+ impurity region 36 as a source and drain region is formed. Using resist film 4 as a mask, Boron (B) ions are implanted into the source/drain formation region of a PMOS transistor.
Finally, as shown in FIG. 58, a p.sup.+ impurity region 37 is formed as a source/drain region. After removal of resist film 4, an interlayer insulating film 7 is formed on the entire surface. After interlayer insulating film 7 is provided with contact holes, a metal interconnection layer 8 to be electrically in contact with each source and drain region. In a device of SOI structure, a so-called multi layer interconnection structure is usually formed by providing additional insulator layers and interconnection layers.
A method of forming a semiconductor device having a conventional SOI structure has been described, and the result of inspection as to the crystal property of SOI in this manufacturing process is schematically illustrated in FIGS. 59 and 60. FIG. 59 illustrates the result of invertors' observation on the surface of monocrystalline silicon layer 3 in the process shown in FIG. 48. As described above, other crystal defects are scarcely observed except for the existence of sub-grain boundaries 31 with its positions controlled to be under the anti reflection films. The density of crystal defect is equal to or smaller than 10.sup.4 cm.sup.-2, which is about the same as a silicon monocrystalline substrate of a usual bulk. Meanwhile, FIG. 60 illustrates the result of observation on the surface of monocrystalline silicon layer 3 immediately after underlying oxide film 17 is formed on monocrystalline silicon layer 3 in the process shown in FIG. 49. According to FIG. 60, a number of crystal defects 19 extending in a certain direction starting from the sub-grain boundaries 31 are newly generated.
The inventors discovered that such new crystal defects are generated both when heat-treatment (annealing in an non-oxide atmosphere) immediately after the formation of a monocrystalline silicon layer and when the monocrystalline silicon layer is oxidized starting from sub-grain boundaries or grain boundaries. The defects are as shown in FIG. 60 generated along the direction &lt;110&gt; (or the direction &lt;111&gt;). It was demonstrated that more defects are generated when the monocrystalline silicon layer is oxidized than heat-treated. The defect is produced in a form of line as shown in FIG. 60. The density of defect is about 3.times.10 cm.sup.-2 in the case of the layer subjected to oxidation, and 10.sup.-4 cm.sup.-2 in the case of the layer subjected only to heat-treatment. This indicates that the new crystal defects result from the movement of point defects such as excess silicon or empty lattices existing in the grain boundaries or sub-grain boundaries immediately after the formation of monocrystalline silicon layer in association with stresses given in oxidation or annealing process (the defects which exist as point defects or forms planes to be layered dislocation defects). Emergence of such crystal defects would cause the properties of the active devices to be significantly uneven. For example, the threshold voltage (Vth) or current driving capability, etc. of an MOS transistor would be increased by the existence of the crystal defects. With such defect being produced crossing the channel region, an impurity diffuses along the defect, resulting in an critical defect of source-drain conduction, thus causing malfunction of the MOS transistor. It is therefore necessary to prevent such defects from being produced in order to achieve higher performances by active devices of SOI structure.
(A), (B), and (C) in FIG. 61 are plan views corresponding to FIGS. 49, 52, and 58, respectively. FIGS. 49, 52, and 58 show cross sections taken along lines X--X in (A), (B) and (C) in FIG. 61, respectively. As shown in (A) in FIG. 61, it is observed that a large number of crystal defects 19 are newly generated extending along a fixed direction starting from the sub-grain boundaries 31. Thereafter, when a thick isolation oxide film 171 is formed in a region surrounding a monocrystalline silicon layer 39 in an MOS transistor formation region shown in (B) in FIG. 61, the sub-grain boundaries are absorbed into the isolation oxide film. However, the crystal defects 19 increase by thermal treatment thereof, and remain within the monocrystalline silicon layer 39 in the MOS transistor formation region. Finally, after a gate electrode 61 is formed, and an n.sup.+ impurity region 36 and a p.sup.+ impurity region 37 are formed as source/drain regions, the crystal defects 19 remain extending in the source/drain regions and the channel region.
Furthermore, the inventors found that when monocrystalline silicon layer 3 is polished for reducing the steps and recesses on its surface immediately after monocrystalline silicon layer 3 is formed as shown in FIG. 48, new crystal defects 19 are produced with sub-grain boundaries 31 as the starting point as similar to the one shown in FIG. 60. These defects are not observed before polishing the surface of the monocrystalline silicon layer, and, therefore, they would be formed in the polishing step. The defects not only increase the unevenness in the device properties such as current driving capability, threshold voltage, etc. but also causes a critical defect such as increase of current leakage.
As described above, the crystal defects produced extended from the sub-grain boundaries remaining in the semiconductor device of an SOI structure will give the following effects. For example, when integrated memory cells are formed in the semiconductor device of the SOI structure, all the memory cells cannot satisfy the same characteristic. The operating speeds of all the memory cells are not uniform, and there exist memory cells having low operation speeds out of the specification. This degrades the manufacturing yield for the semiconductor devices.
For example, if the device is a memory for use in a computer, because of the differences in characteristics of the various transistors it becomes impossible to accurately read stored data from the memory. To the extent that the memory cells are functional, performance is low and operating speed of products using such devices is slow.